A conventional DRAM circuit usually has access time shift problems, and the access time shift problems may lead to low DRAM data output effectiveness. The access time shift problems are usually caused by voltage drops, and are usually solved by elongating power buses or by increasing the quantity of capacitors.
However, as the required working frequency increases, and the required chip size decreases, it becomes increasingly difficult to elongate the power buses and increase the quantity of the capacitors. Therefore, it is necessary to find a solution to the access time shift problems that does not depend on elongating the power buses or increasing the quantity of the capacitors.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.